Job Responsibilities：
• Design and develop Low Dropout Regulators (LDO) for power management ICs
• Define LDO architecture, including error amplifier, pass device, and compensation schemes
• Perform circuit simulations (DC / AC / Transient / Noise / PSRR / Stability)
• Conduct PVT (Process / Voltage / Temperature) and Monte Carlo analysis to ensure robustness and yield
• Collaborate with layout engineers on floorplanning and layout implementation; perform post-layout simulations including parasitic effects
• Support silicon validation, debugging, and bench/ATE measurements

Qualifications Required：
• Master’s degree or above in Electrical Engineering, Electronics, or related field (Bachelor’s with strong experience will be considered)
• Solid background in analog IC design (MOS operation, small-signal analysis)
• Hands-on experience with simulation tools such as Cadence, Spectre, or HSPICE
• Understanding of LDO or Power Management IC design principles
• Strong knowledge of stability analysis (loop gain, phase margin, compensation techniques)

Preferred：
• Tape-out experience, especially in PMIC or LDO design
• Familiarity with Bandgap reference, Charge Pump, DC-DC converters
• Knowledge of ESD, reliability, and layout matching techniques
• Experience in silicon validation and lab debugging (e.g., load transient, line/load regulation)
• Familiarity with CMOS or BCD process technologies

Soft Skills：
• Passion for analog circuit design and continuous learning
• Strong problem-solving and analytical skills
• Ability to work independently and collaboratively in a team environment
• Detail-oriented, responsible, and able to work under project deadlines

工作經驗：經歷不拘
學歷限制：碩士

休假制度：依公司規定